One of the key steps in the manufacture of a semiconductor device is formation of a gate electrode which will hereafter be referred to as the gate. The gate length which is the horizontal measurement between vertical sidewalls of the gate is typically one of the smallest dimensions in the device. The gate length is a critical dimension (CD) since the performance of the resulting device is related to its size. Gate lengths of less than 100 nm are currently required to meet the demand for a faster transistor speed in advanced technologies. A high performance also requires that the gate length or CD must be controlled within a tight specification, typically within a 3 to 5 nm variation across the wafer.
A hard mask is typically an inorganic layer formed on a substrate such as polysilicon to protect the substrate during processes that are used to define a pattern in an overlying photoresist and to provide etch selectivity for transferring the pattern into the substrate during a plasma etch step. Three of the more common hard mask materials are SiXOY hereafter referred to as silicon oxide, silicon nitride, and a composite of the formula SiXOYNZ hereafter referred to as silicon oxynitride.
A lithography process involving an exposure comprised of one or more wavelengths selected from a range of about 10 nm to about 450 nm is initially used to transfer a pattern from a patterned mask containing opaque regions such as chrome on a transparent substrate like quartz into a photoresist layer. Exposed regions of the photoresist undergo a chemical change that renders them soluble in an aqueous base developer when the photoresist is a positive tone material. Unexposed regions remain insoluble and are not removed by developer. As a result, openings in the photoresist layer expose an underlying layer such as a hard mask. In the example of a gate pattern, photoresist lines separated by spaces of varying width are formed. Subsequent steps involve etch transferring the “gate” pattern through the hard mask layer and using the hard mask to etch the pattern into a polysilicon or amorphous silicon substrate to form gates.
The gate length is typically less than the smallest line width that a photolithography process can print in a photoresist layer. As a result, the photoresist line is typically trimmed with a dry etch process in a plasma tool to reduce the CD of the gate length. Even with a trimming process, the CD is sometimes larger than the desired size for the gate length.
To compensate for the larger CD, a conventional method is to adjust the ion implantation dosage for forming lightly doped source/drain regions which will change the ISAT level. However, if the hard mask etch is not controlled to produce CD values within a tight specification range, then the devices based on varying gate lengths will still have an unacceptable range of performance. Therefore, an improved hard mask etch or trim is needed that can control the final gate length CD to within a tight specification that is typically 3 to 5 nm across a wafer.
U.S. Pat. No. 6,197,687 discloses a process by which the CD of the polysilicon gate is reduced by means of plasma etching a photoresist layer that is positioned under a photoactive layer. A final CD of as small as 70 nm can be achieved. However, no mention is made about the ability to control the CD to within a few nm.
U.S. Pat. No. 6,235,609 discloses a method to controllably reduce the CD of a nitride layer in forming shallow trench isolation regions. Either a phosphoric acid treatment or a dry etch in a plasma may be used. As much as 100 nm can be removed from each edge in this process. However, the ability to control the CD to within 3 to 5 nm is not claimed.
U.S. Pat. Nos. 6,060,377 and 6,211,044 to Advanced Micro Devices, Inc. disclose an annealing process that forms a metal suicide layer on the sidewall of a polysilicon structure. The metal silicide is removed by a wet etch to give a polysilicon CD that is smaller than its original dimension prior to the metal deposition and annealing. However, no details are provided about the amount of CD reduction in nm or how well the CD reduction is controlled.
M. Miyashita, T. Tsuga, K. Makihara, and T. Ohmi describe in “Dependence of Surface Microroughness of CZ, FZ, and Epi Wafers on Wet Chemical Process” in J. Electrochem. Soc., Vol. 139, p. 526 (1992) that NH4OH acts as an etchant of oxide while H2O2 acts as the oxidant in a solution consisting of NH4OH, H2O2, and water, hereafter referred to as “APM”. When nitride is exposed to an APM solution, the surface layer is converted into the form of SiOXNY which is then removed by reacting with the NH4OH etchant.